The present invention relates to a technology effectively applicable to a BGA (Ball Grid Array) type semiconductor device formed by mounting a semiconductor chip over a wiring substrate and a manufacturing method for the semiconductor device.
As one of the configurations of semiconductor devices (semiconductor packages) incorporated in electronic equipment, such as personal computers and cellular phones, a BGA (Ball Grid Array) type semiconductor device formed by mounting a semiconductor chip over a wiring substrate (printed wiring substrate) is known.
As one of examples of the configurations of wiring substrates, there is that disclosed in Japanese Unexamined Patent Publication No. 2003-124632 (Patent Document 1). This wiring substrate is formed by: laminating prepreg, obtained by impregnating glass cloth 14 with insulating resin 15 mixed with filler, and copper foil over a wiring substrate 10 in which a first wiring layer 12 is formed on both sides of an insulating substrate 11; thereby forming an insulating layer 21 and surface copper foil 22; patterning the surface copper foil 22 to form a surface copper foil opening 23; and applying a laser beam through the surface copper foil opening 23 to form a hole 16 for via hole having a glass cloth protruded portion 14a. 
As another example of the configurations of wiring substrates, there is that disclosed in Japanese Unexamined Patent Publication No. 2006-196656 (Patent Document 2). This wiring substrate is formed by: forming a first wiring 106a including a semiconductor chip connecting terminal and a first interlayer connecting terminal 101 over a core substrate 100 as an insulating layer on the side where a semiconductor chip is to be mounted; forming a second wiring 106b including a second interlayer connecting terminal 103 on the opposite side of the core substrate 100; electrically coupling together the first interlayer connecting terminal and the second interlayer connecting terminal through a first via hole 102 for interlayer coupling (hereafter, referred to as first via hole) in the core substrate 100; forming an insulating layer 104 on the side of the core substrate 100 where the second wiring is formed; forming a third wiring 106c including a third interlayer connecting terminal over the insulating layer 104; and electrically coupling together the second interlayer connecting terminal and the third interlayer connecting terminal through a second blind via hole 108 for interlayer coupling (hereafter, referred to as second via hole).
As a further example of the configurations of wiring substrates, there is that disclosed in Japanese Unexamined Patent Publication No. 2003-86941 (Patent Document 3). In this wiring substrate, the outermost insulating resin layer 2b is formed as a layer predominantly comprised of resin that does not contain glass cloth 4 as base material. In addition, the second outermost insulating resin layer 2a is formed as a layer containing glass cloth 4 as base material.
[Patent Document 1]    Japanese Unexamined Patent Publication No. 2003-124632
[Patent Document 2]    Japanese Unexamined Patent Publication No. 2006-196656
[Patent Document 3]    Japanese Unexamined Patent Publication No. 2003-86941